1. Field of the Invention
The invention generally relates to microelectronic devices, and more particularly to the design and manufacturing of FinFET devices having improved performance characteristics.
2. Description of the Related Art
Thin-silicon-body field effect transistors (FETs) present a challenge to providing a low-resistance conduction path from the contacts to the source and drain electrodes to the intrinsic channel region in between the source and drain electrodes. Typically, one must expand (flair out) the thickness of the body by some distance beyond its egress from beneath the gate to provide adequate electrical conduction. However, if this expansion (flair out) is made more than several body thicknesses away from the gate, then the added resistance from the relatively long line of thin silicon in the extrinsic region adds substantial extrinsic resistance to the device, thereby degrading device performance.
On the other hand, if the expansion (flair out) is made relatively near the gate electrode, then the capacitance between the wide extrinsic region and the gate becomes large thereby increasing gate capacitance, which then causes degradation in device performance. For example, outer-fringe gate-drain capacitance (Cof) can be high in FinFET devices, which degrades device performance. Some conventional approaches have relied on means of tapering or stepping the width of the silicon as it exits the gate. The tapered designs typically rely on damascene gates, while the stepped-width designs have typically required multiple spacers and silicon growths or depositions. While these solutions have provided a possible solution to the low gate capacitance and low extrinsic resistance trade-off, the actual design and fabrication of such structures capable of achieving this trade-off has been extremely difficult and quite expensive.
FIGS. 1 and 2 illustrate an example of a conventional FinFET device 1. As shown in FIGS. 1 and 2, the conventional FinFET device 1 comprises a substrate 10 with a buried oxide (BOX) layer 15 over the substrate 10. On top of the BOX layer 15 there are source/drain regions 20 with a gate 30 disposed therebetween. Furthermore, the gate 30 contacts the BOX layer 15. A plurality of fins 35 are formed within and transverse to the gate 30. Additionally, an oxide capping layer 25 is formed over the source/drain regions 20 as well as over the fins 35.
The industry has recognized that a compromise must be made between the low extrinsic resistance and the low gate capacitance in such structures (for example the FinFET device 1) to alleviate the degraded performance characteristics conventionally found in these devices. However, until now no known adequate solution has been designed and fabricated. Therefore, there remains a need for a novel method and structure, which provides superior FinFET device performance while simultaneously achieving the low extrinsic resistance and low gate capacitance trade-off.